Semiconductor memory devices, such as dynamic random access memories (DRAMs) are included in an array of programmable memory cells for purposes of storing and accessing data. The DRAM cell includes a field effect transistor (FET) and a storage capacitor. Information is stored on the capacitor either in a charged state or discharged state. The FET provides access to the capacitor during read and write operations. Additionally, the DRAM cell periodically is refreshed to retain the proper state, because of potential leakage in the capacitor.
The configuration of a DRAM memory array is typically robust, and is capable of being accessed for read, write, and refresh operations with very low error rates. However, a memory cell is susceptible to various types of errors that may not be shown as a defect in the cell, but are due to factors that influence the memory cell at one particular time. As such, the state of a memory cell may be affected by noise, soft error rates, leakage, and other factors that may result in data loss.
For instance, non-defect related errors, including soft errors, are due to electrical, magnetic, or other interferences affecting the memory cell. These errors may be due to internal or external generation of noise and/or radiation. For instance, these errors may be due to background radiation generated from a material decay in a chip resulting in stray alpha particles randomly hitting a memory cell, or cosmic radiation (e.g., noise) due to very high energy particles originating from outer space that are hitting memory cells in an array. Also, with higher densities of cells in a memory array, the possibility of noise related disturbs of individual memory cells increases. More particularly, these random electrical occurrences may affect the stored charge on the capacitor of the DRAM memory cell, and cause the memory cell to change state. As such, these errors may not necessarily be due to a defect in the cell construction, however, the information stored on the DRAM memory cell may be incorrect.
On the one hand, because the data loss due to non-defect related errors is not fatal to the memory, the memory cell may be corrected to properly store the valid state of the memory cell after the error is discovered. However, the ability to correct comes with the added penalty of increased circuit complexity, increased chip size, increased power usage, and/or reduced access time. On the other hand, the data loss may result in improper execution of an application or a system crash, since it may change an instruction or data value. In that case, although the memory system is fully functional, the underlying application and/or data has been damaged and may require correction of the states of the affected memory cells. For instance, the affected memory cells may be rewritten (e.g., through error detection and correction techniques), or the system may be rebooted in order to resuscitate a crashed application by repopulating the information in the memory array.
Also, latent defects may adversely affect a memory cell by increasing the rate of signal loss and increasing the probability of soft errors. For instance, one or more latent defects may weaken a memory cell over time, bringing that cell closer to a point of failure. A cell with a latent defect may operate on the margins of failure and not fail under normal operating conditions. However, that cell, when compared to stronger cells without latent defects, may be more prone to soft errors when exposed to the previously discussed interferences (e.g., electrical, magnetic, etc.).
It is desirous to provide a memory array that is less susceptible to non-defect errors, such as, noise, soft errors, etc.